`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   12:05:15 04/02/2011
// Design Name:   NbitPipelinedAdder
// Module Name:   C:/peter/enee408/project/FIRfilter/NbitPipielinedAdder_tb.v
// Project Name:  FIRfilter
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: NbitPipelinedAdder
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module NbitPipielinedAdder_tb;

	parameter N=16;

	// Inputs
	reg [N-1:0] x_in;
	reg [N-1:0] y_in;
	reg c_in;
	reg clock;

	// Outputs
	wire [N-1:0] s_out;
	wire c_out;

	// Instantiate the Unit Under Test (UUT)
	NbitPipelinedAdder #(.N(N)) uut (
		.x_in(x_in), 
		.y_in(y_in), 
		.c_in(c_in), 
		.s_out(s_out), 
		.c_out(c_out), 
		.clock(clock)
	);

	initial begin
	$monitor($time,, "a_in = %d, b_in=%d      s_out=%d"	, x_in, y_in, s_out);
		// Initialize Inputs
		x_in = 0;
		y_in = 0;
		c_in = 0;
		clock = 1;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		x_in = 0;
		y_in = 0;
		#10;
		
		x_in = 10;
		y_in = 10;
		#10;
		
		x_in = 111;
		y_in = 144;
		#10;
		
		x_in = 23;
		y_in = 36;
		#10;
		
		x_in = 67;
		y_in = 69;
		#10;
		
		x_in = 91;
		y_in = 62;
		#10;

	end
	
	always begin
		#5 clock <= ~clock;
	end
      
endmodule

